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KSZ8051MLL 10base-t/100base-tx physical layer transceiver data sheet rev. 1.0 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com july 2010 m9999-071210-1.0 general description the KSZ8051MLL is a single-supply 10base-t/100base- tx ethernet physical layer transceiver for transmission and reception of data over standard cat-5 unshielded twisted pair (utp) cable. the KSZ8051MLL is a highly-integrated, compact solution. it reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2v core. the KSZ8051MLL offers the media independent interface (mii) for direct connection with mii-compliant ethernet mac processors and switches. the KSZ8051MLL provides diagno stic features to facilitate system bring-up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between KSZ8051MLL i/os and board. micrel linkmd ? tdr-based cable diagnostics permit identification of faulty copper cabling. remote and local loopback functions provide verification of analog and digital data paths. the KSZ8051MLL is available in the 48-pin, lead-free lqfp package (see ordering information ). data sheets and support documentation can be found on micrel?s web site at www.micrel.com . features ? single-chip 10base-t/100base-tx ieee 802.3 compliant ethernet transceiver ? mii interface support ? back-to-back mode support for 100mbps copper repeater or media converter ? mdc/mdio management interface for phy register configuration ? programmable interrupt output ? led outputs for link, activity and speed status indication ? on-chip termination resistors for the differential pairs ? baseline wander correction ? hp auto mdi/mdi-x for reliable detection and correction for straight-thr ough and crossover cables with disable and enable option ? auto-negotiation to automatically select the highest link up speed (10/100 mbps) and duplex (half/full) ? power-down and power-saving modes ? linkmd ? tdr-based cable diagnostics for identification of faulty copper cabling ? parametric nand tree support for fault detection between chip i/os and board. ? loopback modes for diagnostics ? single 3.3v power supply with vdd i/o options for 1.8v, 2.5v, or 3.3v ? built-in 1.2v regulator for core ? available in 48-pin (7mm x 7mm) lqfp package ____________________________________________________________________________________________________________ functional diagram
micrel, inc. KSZ8051MLL july 2010 2 m9999-071210-1.0 applications ? game console ? ip phone ? ip set-top box ? ip tv ? lom ? printer ordering information part number temperature range package lead finish description KSZ8051MLL 0c to + 70c 48-pin lqfp pb-free mii, commercial temperature KSZ8051MLLi (1) ? 40c to + 85c 48-pin lqfp pb-free mii, industrial temperature note: 1. contact factory for lead time.
micrel, inc. KSZ8051MLL july 2010 3 m9999-071210-1.0 revision history revision date summary of changes 1.0 6/22/10 data sheet created.
micrel, inc. KSZ8051MLL july 2010 4 m9999-071210-1.0 contents general desc ription ............................................................................................................ .................................................. 1 features ....................................................................................................................... .......................................................... 1 functional diagram............................................................................................................. .................................................. 1 applicat ions................................................................................................................... ........................................................ 2 ordering info rmation ........................................................................................................... ................................................. 2 revision hi story............................................................................................................... ..................................................... 3 contents....................................................................................................................... .......................................................... 4 list of figures........................................................................................................................................................................ 6 list of tables ................................................................................................................. ........................................................ 7 pin configurati on ? ksz8 051mll ................................................................................................. ...................................... 8 pin description ? KSZ8051MLL ................................................................................................... ........................................ 9 pin description ? ksz8 051mll (con tinued)....................................................................................... ............................. 10 pin description ? ksz8 051mll (con tinued)....................................................................................... ............................. 11 pin description ? ksz8 051mll (con tinued)....................................................................................... ............................. 12 strapping options ? KSZ8051MLL ................................................................................................. ................................... 13 functional description: 10base -t/100base-tx transceiver ....................................................................... .................. 14 100base-tx transm it....................................................................................................................................................... 14 100base-tx receive............................................................................................................. ........................................... 14 10base-t tr ansmit ........................................................................................................................................................... 14 10base-t re ceive ............................................................................................................................................................ 14 scrambler/de-scrambler (100base-tx only) ....................................................................................... ........................... 15 sqe and jabber function (10base-t only)........................................................................................ ............................. 15 pll clock synthesizer.......................................................................................................... ............................................ 15 auto-negot iation ............................................................................................................... ................................................ 15 mii data in terface ............................................................................................................. ................................................... 16 mii signal de finition.......................................................................................................... ................................................ 17 transmit cl ock (txc) ........................................................................................................... ........................................ 17 transmit e nable (t xen) .............................................................................................................................................. 17 transmit data [3 :0] (txd[3:0]) ................................................................................................. .................................... 17 receive clock (rxc)............................................................................................................ ........................................ 17 receive data valid (r xdv).......................................................................................................................................... 17 receive data[3:0 ] (rxd[3:0]) ................................................................................................... .................................... 18 receive error (rxer) ........................................................................................................... ....................................... 18 carrier sens e (crs) ............................................................................................................ ........................................ 18 collision (col) ............................................................................................................................................................. 18 mii signal diagram ............................................................................................................. .............................................. 18 back-to-back mode ? 100mbps copp er repeater / me dia converter.................................................................. .......... 19 mii back-to-back m ode (ksz8051m ll only) ........................................................................................ ........................... 19 mii management (m iim) interface................................................................................................ ....................................... 20 interrupt (intrp) .............................................................................................................. ................................................... 20
micrel, inc. KSZ8051MLL july 2010 5 m9999-071210-1.0 hp auto md i /mdi-x .............................................................................................................. ............................................... 21 straight cable ................................................................................................................. .................................................. 21 crossover cable ................................................................................................................ ............................................... 22 linkmd ? cable dia gnostics.............................................................................................................. .................................. 22 nand tree support .............................................................................................................. .............................................. 23 nand tree i/o testing..................................................................................................................................................... 24 power management ............................................................................................................... ............................................. 25 power saving m ode.............................................................................................................. ............................................ 25 energy detect po wer-down mode .................................................................................................. ................................. 25 power-down mode ................................................................................................................ ........................................... 25 slow oscilla tor mode ........................................................................................................... ............................................. 25 reference circuit for powe r and ground connect ions ............................................................................. ..................... 26 register map................................................................................................................... ..................................................... 27 register de scription ........................................................................................................... ................................................ 27 register descript ion (continued)............................................................................................... ....................................... 28 register descript ion (continued)............................................................................................... ....................................... 29 register descript ion (continued)............................................................................................... ....................................... 30 register descript ion (continued)............................................................................................... ....................................... 31 register descript ion (continued)............................................................................................... ....................................... 32 register descript ion (continued)............................................................................................... ....................................... 33 register descript ion (continued)............................................................................................... ....................................... 34 register descript ion (continued)............................................................................................... ....................................... 35 register descript ion (continued)............................................................................................... ....................................... 36 absolute maximum ratings (1) ............................................................................................................................................ 37 operating ratings (2) ............................................................................................................................................................ 37 electrical characteristics (3) ................................................................................................................................................ 37 electrical characteristics (3) (continued) ................................................................................................................... ........ 38 timing di agrams ................................................................................................................ ................................................. 39 mii sqe timing (10bas e-t) ............................................................................................................................................. 39 mii transmit timi ng (10base-t) ................................................................................................. ...................................... 40 mii receive timi ng (10base-t) .................................................................................................. ...................................... 41 mii transmit timi ng (100bas e-tx) .................................................................................................................................. 42 mii receive timi ng (100bas e-tx) ................................................................................................................................... 43 auto-negotiati on timi ng ........................................................................................................ ........................................... 44 mdc/mdio timing ................................................................................................................ ........................................... 45 reset timing................................................................................................................... .................................................. 46 reset ci rcuit .................................................................................................................. ...................................................... 47 reference circuits fo r led strapp ing pins...................................................................................... ................................ 48 magnetics speci fication ........................................................................................................ ............................................. 49 reference clock ? conne ction and se lection..................................................................................... ............................. 50 package info rmation............................................................................................................ ............................................... 51
micrel, inc. KSZ8051MLL july 2010 6 m9999-071210-1.0 list of figures figure 1. auto-negotiation flow chart......................................................................................... .................................. 16 figure 2. ksz8051m ll mii interface............................................................................................ ................................. 18 figure 3. KSZ8051MLL and ksz8041ftl back-to-back m edia conv erter .............................................................. .... 19 figure 4. typical stra ight cable connection ................................................................................... .............................. 21 figure 5. typical cros sover cable connection .................................................................................. ........................... 22 figure 6. KSZ8051MLL powe r and ground connections ............................................................................. ................ 26 figure 7. mii sqe timing (10base-t) ........................................................................................... ................................ 39 figure 8. mii transm it timing (1 0base-t) ...................................................................................... ............................... 40 figure 9. mii receiv e timing (10base-t) ....................................................................................... ............................... 41 figure 10. mii transmi t timing (100base-tx)................................................................................... ............................ 42 figure 11. mii receiv e timing (100base-tx).................................................................................... ............................ 43 figure 12. auto-negotiation fa st link pulse (flp) ti ming ...................................................................... ..................... 44 figure 13. mdc/ mdio timing.................................................................................................... .................................... 45 figure 14. re set timing................................................................................................................................................. 46 figure 15. recommen ded reset circuit.......................................................................................... .............................. 47 figure 16. recommended reset circuit for in terfacing with cpu/fp ga reset output............................................... . 47 figure 17. reference circui ts for led st rapping pins.......................................................................... ......................... 48 figure 18. 25mhz crystal / oscillator reference cl ock connection .............................................................. ............... 50
micrel, inc. KSZ8051MLL july 2010 7 m9999-071210-1.0 list of tables table 1. mii si gnal definition ................................................................................................ ......................................... 17 table 2. mii signal connection for mii back -to-back mode (100base-tx copper repeater)...................................... 19 table 3. mii management fr ame format ? for ksz 8051mll......................................................................... .............. 20 table 4. mdi/mdi- x pin definition ............................................................................................. .................................... 21 table 5. nand tree test pin order ? fo r KSZ8051MLL............................................................................ ................... 23 table 6. KSZ8051MLL po wer pin desc ription..................................................................................... .......................... 26 table 7. mii sqe timing (10base-t) parameters ................................................................................. ........................ 39 table 8. mii transmit ti ming (10base-t) parameters ............................................................................ ...................... 40 table 9. mii receive timi ng (10base-t) parameters ............................................................................. ...................... 41 table 10. mii transmit ti ming (100base-tx ) parameters ......................................................................... ................... 42 table 11. mii receive timi ng (100base-tx) parameters .......................................................................... ................... 43 table 12. auto-negotiation fast li nk pulse (flp) ti ming para meters ............................................................ ............. 44 table 13. mdc/mdio timing pa rameters .......................................................................................... ........................... 45 table 14. reset timing parameters ............................................................................................. ................................. 46 table 15. magnetics selection criteria ........................................................................................ .................................. 49 table 16. qualified singl e port 10/100 magnetics.............................................................................. ........................... 49 table 17. 25mhz crystal / refe rence clock selection criteria .................................................................. ................... 50
micrel, inc. KSZ8051MLL july 2010 8 m9999-071210-1.0 pin configuration ? KSZ8051MLL 48-pin (7mm x 7mm) lqfp
micrel, inc. KSZ8051MLL july 2010 9 m9999-071210-1.0 pin description ? KSZ8051MLL pin number pin name type (1) pin function 1 gnd gnd ground 2 gnd gnd ground 3 gnd gnd ground 4 vdd_1.2 p 1.2v core v dd (power supplied by KSZ8051MLL) decouple with 2.2uf and 0.1uf capacitors to ground, and join with pin 31 by power trace or plane. 5 nc - no connect 6 nc - no connect 7 vdda_3.3 p 3.3v analog v dd 8 nc - no connect 9 rxm i/o physical receive or transmit signal (- differential) 10 rxp i/o physical receive or transmit signal (+ differential) 11 txm i/o physical transmit or receive signal (- differential) 12 txp i/o physical transmit or receive signal (+ differential) 13 gnd gnd ground 14 xo o crystal feedback ? for 25 mhz crystal this pin is a no connect if oscillator or external clock source is used. 15 xi i crystal / oscillator / external clock input 25mhz +/-50ppm 16 rext i set phy transmit output current connect a 6.49k resistor to ground on this pin. 17 gnd gnd ground 18 mdio i/o management interface (mii) data i/o this pin has a weak pull-up, is open-drain like, and requires an external 1.0k pull-up resistor. 19 mdc i management interface (mii) clock input this clock pin is synchronous to the mdio data pin. 20 rxd3 / phyad0 ipu/o mii mode: mii receive data output[3] (2) / config mode: the pull-up/pull-down va lue is latched as phyaddr[0] at the de-assertion of reset. see strapping options section for details. 21 rxd2 / phyad1 ipd/o mii mode: mii receive data output[2] (2) / config mode: the pull-up/pull-down va lue is latched as phyaddr[1] at the de-assertion of reset. see strapping options section for details. 22 rxd1 / phyad2 ipd/o mii mode: mii receive data output[1] (2) / config mode: the pull-up/pull-down va lue is latched as phyaddr[2] at the de-assertion of reset. see strapping options section for details. 23 rxd0 / duplex ipu/o mii mode: mii receive data output[0] (2) / config mode: the pull-up/pull-down va lue is latched as duplex at the de-assertion of reset. see strapping options section for details. 24 gnd gnd ground 25 vddio p 3.3v, 2.5v or 1.8v digital v dd
micrel, inc. KSZ8051MLL july 2010 10 m9999-071210-1.0 pin description ? KSZ8051MLL (continued) pin number pin name type (1) pin function 26 nc - no connect 27 rxdv / config2 ipd/o mii mode: mii receive data valid output / config mode: the pull-up/pull-down value is latched as config2 at the de-assertion of reset. see strapping options section for details. 28 rxc / b-cast_off ipd/o mii mode: mii receive clock output config mode: the pull-up/pull-down valu e is latched as b-cast_off at the de-assertion of reset. see strapping options section for details. 29 rxer / iso ipd/o mii mode: mii receive error output / config mode: the pull-up/pull-down value is latched as isolate at the de-assertion of reset. see strapping options section for details. 30 gnd gnd ground 31 vdd_1.2 p 1.2v core v dd (power supplied by KSZ8051MLL) decouple with 0.1uf capacitor to ground, and join with pin 4 by power trace or plane. 32 intrp / nand_tree# ipu/opu interrupt output: pr ogrammable interrupt output this pin has a weak pull-up, is open-drain like, and requires an external 1.0k pull-up resistor. config mode: the pull-up/pull-down va lue is latched as nand tree# at the de-assertion of reset. see strapping options section for details. 33 txc i/o mii mode: mii transmit clock output mii back-to-back mode: mii transmit clock input 34 txen i mii mode: mii transmit enable input 35 txd0 i mii mode: mii transmit data input[0] (3) 36 txd1 i mii mode: mii transmit data input[1] (3) 37 gnd gnd ground 38 txd2 i mii mode: mii transmit data input[2] (3) 39 txd3 i mii mode: mii transmit data input[3] (3) 40 col / config0 ipd/o mii mode: mii collision detect output / config mode: the pull-up/pull-down value is latched as config0 at the de-assertion of reset. see strapping options section for details. 41 crs / config1 ipd/o mii mode: mii carrier sense output / config mode: the pull-up/pull-down value is latched as config1 at the de-assertion of reset. see strapping options section for details.
micrel, inc. KSZ8051MLL july 2010 11 m9999-071210-1.0 pin description ? KSZ8051MLL (continued) pin number pin name type (1) pin function 42 led0 / nwayen ipu/o led output: programmable led0 output / config mode: latched as auto-negotiati on enable (register 0h, bit 12) at the de-assertion of reset. see strapping options section for details. the led0 pin is programmable via register 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11] reserved 43 led1 / speed ipu/o led output: programmable led1 output / config mode: latched as speed (register 0h, bit 13) at the de-assertion of reset. see strapping options section for details. the led1 pin is programmable via register 1fh bits [5:4], and is defined as follows. led mode = [00] speed pin state led definition 10base-t high off 100base-tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11] reserved 44 nc - no connect 45 nc - no connect 46 nc - no connect
micrel, inc. KSZ8051MLL july 2010 12 m9999-071210-1.0 pin description ? KSZ8051MLL (continued) pin number pin name type (1) pin function 47 rst# i chip reset (active low) 48 nc - no connect notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipu/o = input with internal pull-up (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (s ee electrical characteristics for value) during power-up/reset; output pin with intern al pull-up (see electrical characteristics for value) otherwise. 2. mii rx mode: the rxd[3:0] bits are synchronous with rxc. when rxdv is asserted, rxd[3:0] presents valid data to the mac. rxd[3:0] is invalid data from the phy when rxdv is de-asserted. 3. mii tx mode: the txd[3:0] bits are synchronous with txc. when txen is asserted, txd[3:0] presents valid data from the mac. txd[3:0] has no effect on the phy when txen is de-asserted.
micrel, inc. KSZ8051MLL july 2010 13 m9999-071210-1.0 strapping options ? KSZ8051MLL pin number pin name type (1) pin function 22 21 20 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o the phy address is latched at de-assertion of reset and is configurable to any value from 0 to 7. the default phy address is 00001. phy address 00000 is enabled only if the b-cast_off strapping pin is pulled high. phy address bits [4:3] are set to ?00? by default. 27 41 40 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap-in pins are la tched at the de-assertion of reset. config[2:0] mode 000 mii (default) 110 mii back-to-back 001 ? 101, 111 reserved ? not used 29 iso ipd/o isolate mode pull-up = enable pull-down (default) = disable at the de-assertion of reset, this pin value is latched into register 0h bit 10. 43 speed ipu/o speed mode pull-up (default) = 100mbps pull-down = 10mbps at the de-assertion of reset, this pin val ue is latched into register 0h bit 13 as the speed select, and also is latched into r egister 4h (auto-negotiation advertisement) as the speed capability support. 23 duplex ipu/o duplex mode pull-up (default) = half duplex pull-down = full duplex at the de-assertion of reset, this pin value is latched into register 0h bit 8. 42 nwayen ipu/o nway au to-negotiation enable pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation at the de-assertion of reset, this pin value is latched into register 0h bit 12. 28 b-cast_off ipd/o broadcast off ? for phy address 0 pull-up = phy address 0 is set as an unique phy address pull-down (default) = phy address 0 is set as a broadcast phy address at the de-assertion of reset, this pin value is latched by the chip. 32 nand_tree# ipu/opu nand tree mode pull-up (default) = disable pull-down = enable at the de-assertion of reset, this pin value is latched by the chip. note: 1. ipu/o = input with internal pull-up (see electrical charac teristics for value) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (s ee electrical characteristics for value) during power-up/reset; output pin with intern al pull-up (see electrical characteristics for value) otherwise. the strap-in pins are latched at the de-assertion of reset. in some systems, the mac mii receive input pins may drive high/low during power-up or reset, and consequently cause the phy strap-in pins on the mii signals to be latched to the unintended high/low states. in this case, external pull-ups (4.7k) or pull-downs (1.0k) should be added on these phy strap-in pins to ensure the intende d values are strapped-in correctly.
micrel, inc. KSZ8051MLL july 2010 14 m9999-071210-1.0 functional description: 10 base-t/100base-tx transceiver the KSZ8051MLL is an integrated single 3. 3v supply fast ethernet tr ansceiver. it is fully co mpliant with the ieee 802.3 specification, and reduces board cost and simplifies board la yout by using on-chip termination resistors for the two differential pairs and by integrating t he regulator to supply the 1.2v core. on the copper media side, the KSZ8051MLL supports 10base-t and 100base-tx for transmission and reception of data over a standard cat-5 unshielded twis ted pair (utp) cable, and hp auto mdi/mdi-x for reliable detection of and correction for straight-through and crossover cables. on the mac processor side, the KSZ8051MLL offers the media independent interface (mii) for direct connection with mii compliant ethernet mac processors and switches. the mii management bus option gives the mac processor complete access to the KSZ8051MLL control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status change. 100base-tx transmit the 100base-tx transmit function perfor ms parallel-to-serial conversion, 4b/5b encoding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b /5b coding and followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transm itted in mlt3 current output. the output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and co mplies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nr zi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalizati on filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cabl e characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 1 25mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this si gnal is sent through the de-sc rambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data to the mac. 10base-t transmit the 10base-t drivers are incorporated wi th the 100base-tx drivers to allow for transmission using the same magnetic. the drivers perform internal wave-shaping and pre-emphasis, and output 10base-t signals with typical amplitude of 2.5v peak. the 10base-t signals have harmonic contents that are at least 27db below t he fundamental frequency when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are employed. a differential input receiver circuit and a pll performs the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv or with short pulse widths to prevent noise at the rxp and rxm inputs from falsely trigger the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the KSZ8051MLL decodes a data frame. the receive clock is kept active during idle periods in between data reception.
micrel, inc. KSZ8051MLL july 2010 15 m9999-071210-1.0 scrambler/de-scrambler (100base-tx only) the scrambler is used to spread the power spectrum of t he transmitted signal to reduce emi and baseline wander, and the de-scrambler is needed to recover the scrambled signal. sqe and jabber function (10base-t only) in 10base-t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is required as a test of the 10base-t transmit/recei ve path. if transmit enable (txen) is high for more than 20 ms (jabbering), the 10base-t transmitter is disabled and col is asserted high. if txen is then driven low for more than 250 ms, the 10base- t transmitter is re-enabled and col is de-asserted (returns to low). pll clock synthesizer the KSZ8051MLL generates all internal clocks and all external clocks for system timing from an external 25mhz crystal, oscillator, or reference clock. auto-negotiation the KSZ8051MLL conforms to the auto-negotiation protocol, def ined in clause 28 of the ie ee 802.3 specification. auto-negotiation allows utp (unshielded twisted pair) link par tners to select the highest common mode of operation. during auto-negotiation, link partners adv ertise capabilities across the utp link to each other, and then compare their own capabilities with those they received from their link partne rs. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest priority. ? priority 1: 100base-tx, full-duplex ? priority 2: 100base-tx, half-duplex ? priority 3: 10base-t, full-duplex ? priority 4: 10base-t, half-duplex if auto-negotiation is not supported or the KSZ8051MLL link partner is forced to bypass auto-negotiation, then the KSZ8051MLL sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the KSZ8051MLL to establish link by listening for a fi xed signal protocol in the absence of auto-negotiation advertisement protocol. auto-negotiation is enabled by either hardware pin strappi ng (nwayen, pin 42) or software (register 0h, bit 12). by default, auto-negotiation is enabled after power-up or ha rdware reset. afterwards, auto-negotiation can be enabled or disabled by register 0h, bit 12. if auto-negot iation is disabled, the speed is set by register 0h, bit 13, and the duplex is se t by register 0h, bit 8. the auto-negotiation link up process is shown in figure 1.
micrel, inc. KSZ8051MLL july 2010 16 m9999-071210-1.0 figure 1. auto-negotiation flow chart mii data interface the media independent interface (mii) is compliant with th e ieee 802.3 specification. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 15 pins (6 pins for data transmission, 7 pi ns for data reception, and 2 pins for carrier and collision indication). ? 10mbps and 100mbps data rates are supported at both half and full duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4-bit wide, a nibble. by default, the KSZ8051MLL is configured to mii mode after it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 15, 14), or an external 25mhz clock source (oscillator) connected to xi. ? the config[2:0] strapping pins (pins 27 , 41, 40) set to ?000? (default setting).
micrel, inc. KSZ8051MLL july 2010 17 m9999-071210-1.0 mii signal definition table 1 describes the mii signals. refer to clause 22 of the ieee 802.3 specificati on for detailed information. mii signal name direction (with respect to phy, KSZ8051MLL signal) direction (with respect to mac) description txc output input transmit clock (2.5mhz for 10mbps; 25mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data [3:0] rxc output input receive clock (2.5mhz for 10mbps; 25mhz for 100mbps) rxdv output input receive data valid rxd[3:0] output input receive data [3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection table 1. mii signal definition transmit clock (txc) txc is sourced by the phy. it is a continuous clock t hat provides the timing reference for txen and txd[3:0]. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. transmit enable (txen) txen indicates the mac is presenting nibbles on txd[3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and re mains asserted while all nibbles to be transmitted are presented on the mii, and is negated prior to the first txc following the final nibble of a frame. txen transitions synchronous ly with respect to txc. transmit data [3:0] (txd[3:0]) txd[3:0] transitions synchronously with respect to txc. when txen is asserted, txd[3:0] are accepted for transmission by the phy. txd[3:0] is ?00? to indica te idle when txen is de-asserted. values other than ?00? on txd[3:0] while txen is de-asserted are ignored by the phy. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[3:0], and rxer. ? in 10mbps mode, rxc is recovered from the line while carr ier is active. rxc is derived from the phy?s reference clock when the line is idle, or link is down. ? in 100mbps mode, rxc is continuously recovered from t he line. if link is down, rxc is derived from the phy?s reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on rxd[3:0]. ? in 10mbps mode, rxdv is asserted with the first nibble of the sfd (start of frame delimiter), ?5d?, and remains asserted until the end of the frame. ? in 100mbps mode, rxdv is asserted from the first nibbl e of the preamble to the last nibble of the frame. rxdv transitions synchronously with respect to rxc.
micrel, inc. KSZ8051MLL july 2010 18 m9999-071210-1.0 receive data[3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. receive error (rxer) rxer is asserted for one or more rxc periods to indicate that a symbol error (e.g. a coding error that a phy is capable of detecting, and that may otherwise be undetectable by t he mac sub-layer) was detected somewhere in the frame presently being transferred from the phy. rxer transitions synchronously with re spect to rxc. while rxdv is de-assert ed, rxer has no effect on the mac. carrier sense (crs) crs is asserted and de-asserted as follows: ? in 10mbps mode, crs assertion is based on the recept ion of valid preambles. crs de-assertion is based on the reception of an end-of-frame (eof) marker. ? in 100mbps mode, crs is asserted when a start-of-stream delimiter, or /j/k symbol pair is detected. crs is de- asserted when an end-of-stream delimiter, or /t/r symbol pair is detected. additionally, the pma layer de-asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half-duplex mode whenever the transmitter an d receiver are simultaneously active on the line. this is used to inform the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. mii signal diagram the KSZ8051MLL mii pin connections to the mac are shown in figure 2. figure 2. KSZ8051MLL mii interface
micrel, inc. KSZ8051MLL july 2010 19 m9999-071210-1.0 back-to-back mode ? 10 0mbps copper repeater / media converter two KSZ8051MLL devices can be connected back-to-back to form a 100base-tx to 100base-tx copper repeater. a KSZ8051MLL and a ksz8041ftl can be connected back-to-back to provide a low-cost media converter solution. media conversion is between 100base-tx copper and 100base-fx fiber. on the copper side, link up at 10base-t is not allowed, and is blocked during auto-negotiation. figure 3. KSZ8051MLL and ksz8041ftl back-to-back media converter mii back-to-back mode (KSZ8051MLL only) in mii back-to-back mode, a KSZ8051MLL interfaces wi th another KSZ8051MLL, or a ksz8041ftl to provide a complete 100mbps copper repeater, or media converter solution, respectively. the KSZ8051MLL devices are configured to mii back-to-back mode after power-up or reset with the following: ? strapping pin config[2:0] (pins 27, 41, 40) set to ?110? ? a common 25mhz reference clock connected to xi (pin 15) ? mii signals connected as shown in table 2. KSZ8051MLL (100base-tx copper) [device 1] KSZ8051MLL (100base-tx copper) [device 2] pin name pin number pin type pin name pin number pin type rxc 28 output txc 33 input rxdv 27 output txen 34 input rxd3 20 output txd3 39 input rxd2 21 output txd2 38 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txc 33 input rxc 28 output txen 34 input rxdv 27 output txd3 39 input rxd3 20 output txd2 38 input rxd2 21 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output table 2. mii signal connection for mii back -to-back mode (100base-tx copper repeater)
micrel, inc. KSZ8051MLL july 2010 20 m9999-071210-1.0 mii management (miim) interface the KSZ8051MLL supports the ieee 802.3 mii management interface, also known as the management data input / output (mdio) interface. this interface enables upper-layer device, like a mac proc essor, to monitor and control the state of the KSZ8051MLL. an external device with miim capability is used to read t he phy status and/or configure the phy settings. further details on the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates t he clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the aforementioned physical connection that allows the external controller to communicate with one or more phy devices. ? a set of 16-bit mdio registers. registers [0:8] are standard registers, and their func tions are defined per the ieee 802.3 specification. the additional regi sters are provided for expanded functio nality. see ?register map? section for details. as the default, the KSZ8051MLL supports unique phy addresses 1 to 7, and broadcast phy address 0. the latter is defined per the ieee 802.3 specification, and can be used to read/write to a single KSZ8051MLL device, or write to multiple KSZ8051MLL devices simultaneously. optionally, phy address 0 can be disabled as the broadcast addr ess by either hardware pin strapping (b-cast_off, pin 28) or software (register 16h, bit 9) , and assigned as a unique phy address. the phyad[2:0] strapping pins are used to assign a uni que phy address between 0 and 7 to each KSZ8051MLL device. table 3 shows the mii management frame format for the KSZ8051MLL. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z table 3. mii management frame format ? for KSZ8051MLL interrupt (intrp) intrp (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8051MLL phy register. register 1bh, bits [15: 8] are the interrupt control bits to enable and disable the conditions for asserting the intrp signal. register 1bh, bits [7:0] are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading register 1bh. register 1fh, bit 9 sets the interrupt level to acti ve high or active low. the default is active low. the mii management bus option gives the mac processor complete access to the KSZ8051MLL control and status registers. additionally, an interrupt pi n eliminates the need for the processor to poll the phy for status change.
micrel, inc. KSZ8051MLL july 2010 21 m9999-071210-1.0 hp auto mdi/mdi-x hp auto mdi/mdi-x configuration elimi nates the confusion of whether to use a straight cable or a crossover cable between the KSZ8051MLL and its link partner. this feature allows the KSZ8051MLL to us e either type of cable to connect with a link partner that is in either mdi or mdi-x mode. t he auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8051MLL accordingly. hp auto mdi/mdi-x is enabled by default. it is disabled by writing a one to register 1fh, bit 13. mdi and mdi-x mode is selected by register 1fh, bit 14 if hp auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and re ceive data paths is recommended to support auto mdi/mdi-x. table 4 illustrates how the ieee 802.3 standard defines mdi and mdi-x. mdi mdi-x rj-45 pin signal rj-45 pin signal 1 tx+ 1 rx+ 2 tx- 2 rx- 3 rx+ 3 tx+ 6 rx- 6 tx- table 4. mdi/mdi-x pin definition straight cable a straight cable connects a mdi device to a mdi-x device, or a mdi-x device to a mdi device. figure 4 depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi-x). figure 4. typical straight cable connection
micrel, inc. KSZ8051MLL july 2010 22 m9999-071210-1.0 crossover cable a crossover cable connects a mdi device to another mdi devic e, or a mdi-x device to another mdi-x device. figure 5 depicts a typical crossover cable connection between two switches or hubs (two mdi-x devices). figure 5. typical crossover cable connection linkmd ? cable diagnostics the linkmd ? function utilizes time domain reflectometry (tdr) to analyze the cabli ng plant for common cabling problems, such as open circuits, short circuits and impedance mismatches. linkmd ? works by sending a pulse of known amplitude and duration down the mdi or mdi-x pair, and then analyzing the shape of the reflected signal to determine the type of fault. t he time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd ? function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd ? is initiated by accessing register 1dh, the linkmd ? control/status register, in conj unction with register 1fh, the phy control 2 register. the latter register is used to disa ble auto mdi/mdi-x and to select either mdi or mdi-x as the cable differential pair for testing.
micrel, inc. KSZ8051MLL july 2010 23 m9999-071210-1.0 nand tree support the KSZ8051MLL provides parametric nand tree support fo r fault detection between chip i/os and board. the nand tree is a chain of nested nand gates in which each KSZ8051MLL digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the crs pin provides t he output for the nested nand gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving low each nand tree input pin sequentially per the nand tree pin order ? checking the nand tree output to ensure there is a toggl e high-to-low or low-to-high for each nand tree input driven low table 5 lists the nand tree pin order. pin number pin name nand tree description 18 mdio input 19 mdc input 20 rxd3 input 21 rxd2 input 22 rxd1 input 23 rxd0 input 27 rxdv input 28 rxc input 29 rxer input 32 intrp input 33 txc input 34 txen input 35 txd0 input 36 txd1 input 38 txd2 input 39 txd3 input 42 led0 input 43 led1 input 40 col input 41 crs output table 5. nand tree test pin order ? for KSZ8051MLL
micrel, inc. KSZ8051MLL july 2010 24 m9999-071210-1.0 nand tree i/o testing the following procedure can be used to check for faults on the KSZ8051MLL digital i/o pin connections to the board: 1. enable nand tree mode by either hardware pin strapping (nand_tree#, pin 32) or software (register 16h, bit 5). 2. use board logic to drive all KSZ8051MLL nand tree input pins high. 3. use board logic to drive each nand tree input pin, per KSZ8051MLL nand tree pin order, as follow: a. toggle the first pin (mdio) from high to low, and verify the crs pin switch from low to high to indicate that the first pin is connected properly. b. leave the first pin (mdio) low. c. toggle the second pin (mdc) from high to low, and veri fy the crs pin switch from high to low to indicate that the second pin is connected properly. d. leave the first pin (mdio) and the second pin (mdc) low. e. toggle the third pin (rxd3) from high to low, and veri fy the crs pin switch from low to high to indicate that the third pin is connected properly. f. continue with this sequence until all ksz8051m ll nand tree input pins have been toggled (tested). each KSZ8051MLL nand tree input pin must cause the crs output pin to toggle high-to-low or low-to-high to indicate a good connection. if the crs pin fails to toggle when the ksz8051 mll input pin toggles from high to low, the input pin has a fault.
micrel, inc. KSZ8051MLL july 2010 25 m9999-071210-1.0 power management the KSZ8051MLL offers the following power management modes: power saving mode power-saving mode is used to reduce the transceiver powe r consumption when the cable is unplugged. it is enabled by writing a one to register 1fh, bit 10, and is in effect when auto-negotiation mode is enabled and cable is disconnected (no link). in this mode, the KSZ8051MLL shuts down all transceiver blo cks, except for transmitter, energy detect and pll circuits. by default, power-saving mode is disabled after power-up. energy detect power-down mode energy detect power-down mode is used to further reduce the transceiver power consumption when the cable is un- plugged. it is enabled by writing a zero to register 18h, bit 11, and is in effect when auto-negotiation mode is enabled and cable is disconnected (no link). in this mode, the KSZ8051MLL shuts down all transceiver blo cks, except for transmitter and energy detect circuits. further power consumption is achieved by ex tending the time interval in between transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses is needed to ensure two link partners in the same low power state and with auto mdi/mdi-x disabled can wake up when the cable is connected between them. by default, energy detect power-down mode is disabled after power-up. power-down mode power-down mode is used to power down the KSZ8051MLL devic e when it is not in use after power-up. it is enabled by writing a one to register 0h, bit 11. in this mode, the KSZ8051MLL disables all internal fu nctions, except for the mii management interface. the KSZ8051MLL exits (disables) power-down mode afte r register 0h, bit 11 is set back to zero. slow oscillator mode slow oscillator mode is used to disconnect the input referenc e crystal/clock on xi (pin 15) and select the on-chip slow oscillator when the KSZ8051MLL device is not in use after power -up. it is enabled by writing a one to register 11h, bit 5. slow oscillator mode works in conjunction with power-do wn mode to put the KSZ8051MLL device in the lowest power state with all internal functions disabled, except for the mii management interface. to properly exit this mode and return to normal phy operation, use the fo llowing programming sequence: 1. disable slow oscillator mode by writ ing a zero to register 11h, bit 5. 2. disable power-down mode by writi ng a zero to register 0h, bit 11. 3. initiate software reset by writing a one to register 0h, bit 15.
micrel, inc. KSZ8051MLL july 2010 26 m9999-071210-1.0 reference circuit for powe r and ground connections the KSZ8051MLL is a single 3.3v supply device with a built-i n regulator to supply the 1.2v core. the power and ground connections are shown in figure 6 and table 6 for 3.3v vddio. figure 6. KSZ8051MLL power and ground connections power pin pin number description vdd_1.2 4 connect with pin 31 by power trace or plane. decouple with 2.2uf and 0.1uf capacitors to ground. vdda_3.3 7 connect to board?s 3.3v su pply thru ferrite bead. decouple with 22uf and 0.1uf capacitors to ground. vddio 25 connect to board?s 3.3v supply for 3.3v vddio. decouple with 22uf and 0.1uf capacitors to ground. vdd_1.2 31 connect with pin 4 by power trace or plane. decouple with 0.1uf capacitor to ground. table 6. KSZ8051MLL power pin description
micrel, inc. KSZ8051MLL july 2010 27 m9999-071210-1.0 register map register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h link partner next page ability 9h ? 10h reserved 11h afe control 1 12h ? 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h ? 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd ? control/status 1eh phy control 1 1fh phy control 2 register description address name description mode (1) default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loop-back 1 = loop-back mode 0 = normal operation rw 0 0.13 speed select 1 = 100mbps 0 = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw set by speed strapping pin. see ?strapping options? section for details. 0.12 auto- negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiation result overrides settings in register 0.13 and 0.8. rw set by nwayen strapping pin. see ?strapping options? section for details.
micrel, inc. KSZ8051MLL july 2010 28 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default register 0h ? basic control 0.11 power down 1 = power down mode 0 = normal operation if software reset (register 0.15) is used to exit power down mode (register 0.11 = 1), two software reset writes (register 0.15 = 1) are required. first write clears power down mode; second write resets chip and re-latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw set by iso strapping pin. see ?strapping options? section for details. 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw inverse of duplex strapping pin value. see ?strapping options? section for details. 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved ro 000_0000 register 1h ? basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full duplex 1 = capable of 100mbps full-duplex 0 = not capable of 100mbps full-duplex ro 1 1.13 100base-tx half duplex 1 = capable of 100mbps half-duplex 0 = not capable of 100mbps half-duplex ro 1 1.12 10base-t full duplex 1 = capable of 10mbps full-duplex 0 = not capable of 10mbps full-duplex ro 1 1.11 10base-t half duplex 1 = capable of 10mbps half-duplex 0 = not capable of 10mbps half-duplex ro 1 1.10:7 reserved ro 0000 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = capable to perform auto-negotiation 0 = not capable to perform auto-negotiation ro 1
micrel, inc. KSZ8051MLL july 2010 29 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0022h register 3h ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manufacturer?s model number ro 01_0101 3.3:0 revision number four bit manufacturer?s revision number ro indicates silicon revision register 4h ? auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability. rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability rw set by speed strapping pin. see ?strapping options? section for details. 4.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability rw set by speed strapping pin. see ?strapping options? section for details. 4.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability rw 1 4.4:0 selector field [0000 1] = ieee 802.3 rw 0_0001
micrel, inc. KSZ8051MLL july 2010 30 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default register 5h ? auto-negot iation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric & symmetric pause ro 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability ro 0 5.4:0 selector field [0000 1] = ieee 802.3 ro 0_0001 register 6h ? auto-negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection. ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0
micrel, inc. KSZ8051MLL july 2010 31 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default register 7h ? auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow 0 = last page rw 0 7.14 reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? link partner next page ability 8.15 next page 1 = additional next page(s) will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 11h ? afe control 1 11.15:6 reserved rw 0000_0000_00 11.5 slow-oscillator mode enable slow oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on-chip slow oscillator when the ksz8051 device is not in use after power-up. 1 = enable 0 = disable this bit automatically sets software power down to the analog side when enabled. rw 0 11.4:0 reserved rw 0_0000 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h
micrel, inc. KSZ8051MLL july 2010 32 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default register 16h ? operation mode strap override 16.15:11 reserved rw 0000_0 16.10 reserved ro 0 16.9 b-cast_off override 1 = override strap-in for b-cast_off if bit is ?1?, phy address 0 is non-broadcast. rw 0 16.8 reserved rw 0 16.7 mii b-to-b override 1 = override strap-in for mii back-to-back mode (set also bit 0 of this register to 1) rw 0 16.6 reserved rw 0 16.5 nand tree override 1 = override strap-in for nand tree mode rw 0 16.4:1 reserved rw 0000 16.0 mii override 1 = override strap-in for mii mode rw 1 register 17h ? operation mode strap status 17.15:13 phyad[2:0] strap-in status [000] = strap to phy address 0 [001] = strap to phy address 1 [010] = strap to phy address 2 [011] = strap to phy address 3 [100] = strap to phy address 4 [101] = strap to phy address 5 [110] = strap to phy address 6 [111] = strap to phy address 7 ro 17.12:10 reserved ro 17.9 b-cast_off strap-in status 1 = strap to b-cast_off if bit is ?1?, phy address 0 is non-broadcast. ro 17.8 reserved ro 17.7 mii b-to-b strap-in status 1 = strap to mii back-to-back mode ro 17.6 reserved ro 17.5 nand tree strap-in status 1 = strap to nand tree mode ro 17.4:1 reserved ro 17.0 mii strap-in status 1 = strap to mii mode ro
micrel, inc. KSZ8051MLL july 2010 33 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default register 18h ? expanded control 18.15:12 reserved rw 0000 18.11 edpd disabled energy detect power down mode 1 = disable 0 = enable rw 1 18.10 100base-tx preamble restore 1 = restore received preamble to mii output (random latency) 0 = consume 1-byte preamble before sending frame to mii output for fixed latency rw 0 18.9:7 reserved rw 000 18.6 10base-t preamble restore 1 = restore received preamble to mii output 0 = remove all 7-bytes of preamble before sending frame (starting with sfd) to mii output rw 0 18.5:0 reserved rw 00_0000 register 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link down interrupt enable 1= enable link down interrupt 0 = disable link down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/sc 0
micrel, inc. KSZ8051MLL july 2010 34 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occurred ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occurred ro/sc 0 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occurred ro/sc 0 1b.2 link down interrupt 1 = link down occurred 0 = link down did not occurred ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occurred ro/sc 0 1b.0 link up interrupt 1 = link up occurred 0 = link up did not occurred ro/sc 0 register 1dh ? linkmd ? control/status 1d.15 cable diagnostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ? . ro 0 1d.11:9 reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 register 1eh ? phy control 1 1e.15:10 reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro 1e.6 reserved ro 0 1e.5 mdi/mdi-x state 1 = mdi-x 0 = mdi ro 1e.4 energy detect 1 = presence of signal on receive differential pair 0 = no signal detected on receive differential pair ro 0
micrel, inc. KSZ8051MLL july 2010 35 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 1e.2:0 operation mode indication [000] = still in auto-negotiation [001] = 10base-t half-duplex [010] = 100base-tx half-duplex [011] = reserved [100] = reserved [101] = 10base-t full-duplex [110] = 100base-tx full-duplex [111] = reserved ro 000 register 1fh ? phy control 2 1f:15 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = micrel auto mdi/mdi-x mode rw 1 1f:14 mdi/mdi-x select when auto mdi/mdi-x is disabled, 1 = mdi-x mode transmit on rxp,rxm (pins 10,9) and receive on txp,txm (pins 12,11) 0 = mdi mode transmit on txp,txm (pins 12,11) and receive on rxp,rxm (pins 10,9) rw 0 1f:13 pair-swap disable 1 = disable auto mdi/mdi-x 0 = enable auto mdi/mdi-x rw 0 1f.12 reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allow transmitter to send pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7:6 reserved rw 00
micrel, inc. KSZ8051MLL july 2010 36 m9999-071210-1.0 register descrip tion (continued) address name description mode (1) default 1f.5:4 led mode [00] = led1 : speed led0 : link/activity [01] = led1 : activity led0 : link [10], [11] = reserved rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f.2 remote loop-back 1 = remote (analog) loop back is enable 0 = normal mode rw 0 1f.1 enable sqe test 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 note: 1. rw = read/write. ro = read only. sc = self-cleared. lh = latch high. ll = latch low.
micrel, inc. KSZ8051MLL july 2010 37 m9999-071210-1.0 absolute maximum ratings (1) supply voltage (v dd_1.2 ) .................................................. ? 0.5v to + 1.8v (v ddio, v dda_3.3 ) ....................................... ? 0.5v to + 4.0v input voltage (all i nputs) .............................. ? 0.5v to + 4.0v output voltage (all outputs) ......................... ? 0.5v to + 4.0v lead temperature (solde ring, 10sec .) ....................... 260c storage temperature (t s ) ......................... ? 55c to + 150c operating ratings (2) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to + 3.465v (v ddio_2.5 )........................................ +2.375v to + 2.625v (v ddio_1.8 )........................................ +1.710v to + 1.890v ambient temperature (t a , commercial)...................................... 0c to + 70c (t a , industrial) ...................................... ? 40c to + 85c maximum junction temperature (t j max.) ................ 125c thermal resistance ( ja ) .........................................76c/w thermal resistance ( jc ) .........................................15c/w electrical characteristics (3) symbol parameter condition min. typ. max. units supply current (v ddio , v dda_3.3 = 3.3v) (4) i dd1 10base-t full-duplex traffic @ 100% utilization 39.5 ma i dd2 100base-tx full-duplex traffic @ 100% utilization 48.9 ma i dd3 power saving mode ethernet cable discon nected (reg. 1f.10 = 1) 30.0 ma i dd4 power-down mode software power down (reg. 0.11 = 1) 2.0 ma cmos level inputs v ddio = 3.3v 2.0 v v ddio = 2.5v 1.8 v v ih input high voltage v ddio = 1.8v 1.3 v v ddio = 3.3v 0.8 v v ddio = 2.5v 0.7 v v il input low voltage v ddio = 1.8v 0.5 v i in input current v in = gnd ~ vddio -10 10 a cmos level outputs v ddio = 3.3v 2.4 v v ddio = 2.5v 2.0 v v oh output high voltage v ddio = 1.8v 1.5 v v ddio = 3.3v 0.4 v v ddio = 2.5v 0.4 v v ol output low voltage v ddio = 1.8v 0.3 v |i oz | output tri-state leakage 10 a led outputs i led output drive current each led pin (led0, led1) 8 ma strapping pins v ddio = 3.3v 29 43 76 k v ddio = 2.5v 37 59 102 k pu internal pull-up resistance v ddio = 1.8v 57 100 187 k v ddio = 3.3v 27 43 76 k v ddio = 2.5v 35 60 110 k pd internal pull-down resistance v ddio = 1.8v 55 100 190 k
micrel, inc. KSZ8051MLL july 2010 38 m9999-071210-1.0 electrical characteristics (3) (continued) symbol parameter condition min. typ. max. units 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion + 0.25 ns t r , t f overshoot 5 % v set reference voltage of iset 0.65 v output jitter peak-to-peak 0.7 1.4 ns 10base-t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak-to-peak 3.5 ns t r , t f rise/fall time 25 ns 10base-t receive v sq squelch threshold 5mhz square wave 400 mv notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause per manent damage to the device. operation of the device at these or an y other conditions above those specified in the operating sections of this specification is not implied. maximum conditions fo r extended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25 c. specification is for packaged product only. 4. current consumption is for the single 3.3v supply KSZ8051MLL device only, and includes the transmit driver current and the 1 .2v supply voltage (v dd_1.2 ) that are supplied by the KSZ8051MLL.
micrel, inc. KSZ8051MLL july 2010 39 m9999-071210-1.0 timing diagrams mii sqe timing (10base-t) figure 7. mii sqe timing (10base-t) timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de-asserted 1.8 us t sqep col (sqe) pulse duration 1.0 us table 7. mii sqe timing (10base-t) parameters
micrel, inc. KSZ8051MLL july 2010 40 m9999-071210-1.0 mii transmit timing (10base-t) figure 8. mii transmit timing (10base-t) timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 120 ns t su2 txen setup to rising edge of txc 120 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 200 ns t crs2 txen low to crs de-asserted latency 550 ns table 8. mii transmit timing (10base-t) parameters
micrel, inc. KSZ8051MLL july 2010 41 m9999-071210-1.0 mii receive timing (10base-t) figure 9. mii receive timing (10base-t) timing parameter description min. typ. max. unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rxc pulse width high 200 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 185 ns t rlat crs to (rxdv, rxd[3:0]) latency 6.5 us table 9. mii receive timing (10base-t) parameters
micrel, inc. KSZ8051MLL july 2010 42 m9999-071210-1.0 mii transmit timing (100base-tx) figure 10. mii transmit timing (100base-tx) timing parameter description min. typ. max. unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising edge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 35 ns t crs2 txen low to crs de-asserted latency 36 ns table 10. mii transmit timing (100base-tx) parameters
micrel, inc. KSZ8051MLL july 2010 43 m9999-071210-1.0 mii receive timing (100base-tx) figure 11. mii receive timing (100base-tx) timing parameter description min. typ. max. unit t p rxc period 40 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 23 ns t rlat crs to (rxdv, rxd[3:0] latency 130 ns table 11. mii receive timing (100base-tx) parameters
micrel, inc. KSZ8051MLL july 2010 44 m9999-071210-1.0 auto-negotiation timing figure 12. auto-negotiation fast link pulse (flp) timing timing parameter description min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 table 12. auto-negotiation fast link pulse (flp) timing parameters
micrel, inc. KSZ8051MLL july 2010 45 m9999-071210-1.0 mdc/mdio timing figure 13. mdc/mdio timing timing parameter description min. typ. max. unit t p mdc period 400 ns t md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc * [can vary with mdc clock frequency] * ns table 13. mdc/mdio timing parameters
micrel, inc. KSZ8051MLL july 2010 46 m9999-071210-1.0 reset timing the KSZ8051MLL reset timing requirement is summarized in figure 14 and table 14. figure 14. reset timing parameter description min. max. units t sr stable supply voltage (v ddio, v dda_3.3 ) to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap-in pin output 6 ns table 14. reset timing parameters after the de-assertion of reset, it is recommended to wait a minimum of 100s before st arting programming on the miim (mdc/mdio) interface.
micrel, inc. KSZ8051MLL july 2010 47 m9999-071210-1.0 reset circuit figure 15 shows a reset circuit recommended for powering up t he KSZ8051MLL if reset is triggered by the power supply. figure 15. recommended reset circuit figure 16 represents a reset circuit recomm ended for applications where reset is driven by another device (e.g., cpu or fpga). at power-on-reset, r, c and d1 provide the necessary ramp rise time to reset the KSZ8051MLL device. the rst_out_n from cpu/fpga provides the warm reset after power up. figure 16. recommended reset circuit for interfacing with cpu/fpga reset output
micrel, inc. KSZ8051MLL july 2010 48 m9999-071210-1.0 reference circuits fo r led strapping pins the pull-up, float and pull-down reference circuits for t he led1/speed and led0/nwayen strapping pins are shown in figure 17. figure 17. reference circuits for led strapping pins
micrel, inc. KSZ8051MLL july 2010 49 m9999-071210-1.0 magnetics specification a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode chokes is recommended for exceeding fcc requirements. table 15 and table 16 list recommended magnetic char acteristics and qualified magnetics for the KSZ8051MLL. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (max.) -1.0db 100khz ? 100mhz hipot (min.) 1500vrms table 15. magnetics selection criteria magnetic manufacturer part number auto mdi-x number of port bel fuse s558-5999-u7 yes 1 bel fuse (mag jack) si-46001-f yes 1 bel fuse (mag jack) si-50170-f yes 1 delta lf8505 yes 1 lankom lf-h41s-1 yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 tdk (mag jack) tla-6t718a yes 1 table 16. qualified single port 10/100 magnetics
micrel, inc. KSZ8051MLL july 2010 50 m9999-071210-1.0 reference clock ? conn ection and selection a crystal or external clock source, such as an oscillator , is used to provide the reference clock for the KSZ8051MLL. for the KSZ8051MLL in all operating modes, the reference clock is 25mhz. the reference clock connections to xi (pin 15) and xo (pin 14), and the reference clock selection criteria are provided in figure 18 and table 17. figure 18. 25mhz crystal / oscillator reference clock connection characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm table 17. 25mhz crystal / refe rence clock selection criteria
micrel, inc. KSZ8051MLL july 2010 51 m9999-071210-1.0 package information 48-pin (7mm x 7mm) lqfp note: all dimensions are in millimeters. micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel, incor p orated.

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